two full-rate t1/e1 payloads over a single g.shdsl/hdsl2/sdsl link dual-bearer operation the M28946 includes two independent full-rate t1/e1 interfaces, capable of simultaneously carrying two sepa- rate time-synchronized pulse code modulation (pcm) data streams over a single twisted pair. utilizing advanced 32-level pulse amplitude modulation (pam); the M28946 operates at speeds up to 4640, or twice the normal g.shdsl rate, enabling operators to double their line utilization at distances of up to 7,000 feet or 2km. the M28946 offers all of the features provided by the m28975 multi-mode transceiver including multi-pair operation and guaranteed interoperability with legacy systems including hdsl2, sdsl, and mindspeeds autobaud? software. multimode operation the M28946 dsl solution not only complies with the itu g.shdsl standard, it also supports the optional enhanced performance asymmetrical psd (epap) modes of opera- tion. in addition, it complies with the ansi hdsl2 stan- dard (ansi t1.418) and delivers interoperability with mindspeed technologies? market-leading zipwire trans- ceivers through operation in 2b1q multi-rate mode. the 2b1q mode supports autobaud for sdsl interoperability, rate optimization and fast connect times, as well as standards-based hdsl operation. all of these modes are supported by a single hardware circuit (i.e., one trans- former, crystal and hybrid for all modes) and can be configured in real-time via software control. embedded microprocessor the M28946 chipset includes an embedded micro- processor and a full suite of software that facilitates faster and simplified development of systems that comply with all applicable itu, ansi and etsi standards. the embedded microprocessor and software handle the extended operations channel (eoc) processing and many other functions often delegated to an external host controller in competing solutions. this greatly reduces software-porting efforts and eliminates real-time processing requirements for an external host controller. flexible framer the M28946s integrated framer includes fully featured utopia level 2 and pcm interfaces. the utopia interface includes atm tc-layer processing. the framer automati- cally extracts and inserts dsl overhead (i.e., eoc, indi- cator and z-bits, crc, sync word, etc.) and passes it on to the embedded microprocessor. all g.shdsl and hdsl2 frame formats and eoc messaging protocols are supported, as well as other non-standard sdsl frame formats, including framer bypass mode. a conexant business ? > 2 independent full-rate pcm ports for simultaneous operation > double the throughput per copper pair of other solutions > reliable operation at 4640 kbps up to 7,000 or 2km > multi-mode operation > low-power consumption > highly integrated solution > embedded microprocessor > interoperable with zipwire 2b1q transceivers including autobaud > > key features zipwireplus? M28946 g.shdsl transceiver g.shdsl dual-bearer multi-mode transceiver M28946 ( datasheet : )
www.mindspeed.com/salesoffices general information: (949) 579-3000 headquarters C newport beach 4000 macarthur blvd., east tower newport beach, ca 92660-3007 28946-brf-001-a m03-0765 ? 2002 mindspeed technologies ? , a conexant business. all rights reserved. mindspeed and the mindspeed logo are trademarks ofmindspeed technologies. all other trademarks are the property oftheir respective owners. although mindspeed technologies strives for accuracy in all its publications, this material may contain errors or omissions and is subject to change without notice. this material is provided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and non-infringement. mindspeed technologies shall not be liable for any special, indirect, incidental or consequential damages as a result of its use. a conexant business ? ? operating modes supported: - itu g.shdsl including epap modes (itu g.991.2) - itu g.handshake (itu g.994.1) - hdsl2 (ansi t1.418) - sdsl/2b1q (autobaud) - 4640 operation complies with 2b1q spectral masks - proprietary/extended reach (ansi spectrum management for loop transmission systems) - proprietary/high-speed (ansi spectrum management for loop transmission systems) ? highly integrated solution including framer, microprocessor, rom/ram, frequency synthesizer, and dsp ? two packaging options for high density and manufacturability option a(two-package): ? dsp/framer/up = 13x13 mm ? fpbga; afe/ld = 7x7 mm lga option b (two package): ? dsp/framer/up = 24x24 mm ? lqfp; afe/ld = 7 x 7 lga ? embedded microprocessor for autonomous operation and eoc processing ? data rates from 192 kbps to 4.6 mbps in 8 kbps increments ? central office (cot) and remote (rt) operation ? glueless interface to popular microprocessors ? single hardware circuit supports all speeds and modes of operation ? +1.8 v, +3.3 v and +12 v power supplies ? jtag boundary scan ? operation over full industrial t emper- ature range (-40 c to +85 c) applications ? dsl-enabled customer premises equipment (cpe) ? integrated access devices (iads) ? digital subscriber line access multiplexers (dslams) ? n-channel daml and voice pairgain systems ? nx64k data transport ? remote lan access ? t1 and e1 hdsl-enabled transport systems ? cellular base station data links ? campus modems ? data, voice and video transport systems product features full system solution the M28946 pairs up with the m28927-29 integrated analog front end/line driver (afe/ld) to provide a full dsl solution. the inte- grated line driver is capable of driving the high line-power epap modes as specified by the g.shdsl standard. the integrated frequency synthesizer, as with the rest of the zipwireplus family, supports data rates from 192 kbps to 4.6 mbps, and requires only one external crystal. this highly integrated dsl solution enables oems to design and manufacture the most feature-rich, lowest power and highest-density dsl equipment in the industry. multi-level tcpam dsp 8051 core copper pair rom/ram hostport interface host port ram bus afe/ line driver hybrid framer atm/ tc utopia pcm i/f pcm i/f M28946 block diagram
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